Contact

Room
4155
Phone
+49 30 84185-301
Email
Birth name
Tobias Pfender

Projects

Projects as Head

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Automated Validation of System-on-Chip Designs

In the design process of integrated circuits and other electronic hardware, a huge amount of time and resources is spent on the verification of the design and the final...

Automated Validation of System-on-Chip Designs

Projects as Member

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MODAL-SynLab

A major aim of the Research Campus MODAL is the development and use of mathematical synergies between the individual labs of the network. In this context, the fields of...

MODAL-SynLab
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Chip Design Verification with Constraint Integer Programming

In the design process of integrated circuits and other electronic hardware, a huge amount of time and resources is spent on the verification of the design and the final...

Chip Design Verification with Constraint Integer Programming
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Automated Validation of System-on-Chip Designs

In the design process of integrated circuits and other electronic hardware, a huge amount of time and resources is spent on the verification of the design and the final...

Automated Validation of System-on-Chip Designs
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Models and Simulations for Network Planning and Control of UMTS

The deployment of mobile telecommunication networks for the new UMTS standard poses new challenges for radio network planning. In contrast to, for example, GSM, coverage...

Models and Simulations for Network Planning and Control of UMTS